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PK88.AS
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1990-11-14
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10KB
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298 lines
;/*
; * Copyright 1988 by the Radio Amateur Telecommunications Society
; * and Thomas A. Moulton, W2VY
; *
; * This software may only be modified, copied, distributed or
; * executed for non-profit purposes by individuals operating
; * systems in the Amateur Radio Service. Credit to the
; * author(s) and to the Radio Amateur Telecommunications Society
; * must be made in modules where RATS provided software is used,
; * and in any announcements and documentation.
; *
; * As a non-profit, research and development organization, the
; * Radio Amateur Telecommunications Society distributes software
; * in both executable and source forms. This policy is in place
; * to encourage the development and distribution of OSI-based,
; * networking tools. In order to protect the interests of the
; * Society and the authors, we have placed some conditions
; * of use on the software. Other groups are encouraged
; * to place the same or similar guidelines on
; * software they produce.
; *
; * The Radio Amateur Telecommunications Society reserves the right
; * to specify and alter the terms under which software provided by
; * the Society may be used. This policy is consistent with the
; * objective of uniform and consistent "Open Systems Interconnections."
; *
; * All acceptable Amateur Radio related uses of this software
; * will be outlined in the "ROSE Implementer's Guide". Individuals
; * or organizations wishing to add to, or modify the provisions of
; * the guide to accommodate local or evolutionary requirements
; * should document the proposed change(s) and forward them to the
; * Society. If accepted, written notification will be provided by
; * the Society to the submitting organization or individual(s).
; * The Society will then issue a "ROSE Implementer's Guide Change
; * Notice". Periodically, the Society will re-issue the "ROSE
; * Implementer's Guide" and incorporate the text of the change
; * notices. This procedure has been put in to place to ensure
; * compatibility between systems and to ensure their "Openness"
; * and interoperability.
; *
; * No part of this software may be used in other packages
; * without prior authorization from the author or the Society.
; * Software incorporating this module, all or in part, must be
; * provided to the Society prior to distribution or use by
; * anyone not directly involved in testing of the revised
; * environment. Current releases of the combined software must
; * be provided to the Society in both source and executable
; * forms. Adequate documention to produce an executable module
; * from the provided source must also be included.
; *
; * Non-Amateur Radio non-profit uses may be authorized on a case
; * by case basis. Inquiries for such use may be made in writing
; * to the Society. Non-commercial uses consistent with the
; * general principles of Open Systems Interconnection Reference
; * Model will be generally considered with favor.
; *
; * Commercial licensing of the software is also available based
; * on normal commercial terms. Licensing inquiries should be
; * directed to the Society. Commercial licensing of the standard
; * software will be done in situations which materially benefit
; * the Amateur Radio Packet Network. Additional licensing is
; * reserved by the individual authors.
; *
; * The Radio Amateur Telecommunications Society provides this software
; * on an "as is" basis. The Society assumes no liability for
; * loss incurred through the use of this software. Amateur Radio
; * use of this software implies non-commercial and voluntary
; * development, deployment and use of this software in a "Amateur",
; * non-commercial service. Commercial users are encouraged to
; * inspect their copies of the source code. Source code modification
; * licenses are available if a combined Object and Source Code
; * license was not originally established.
; *
; * The Society may be contacted by writing or calling at:
; *
; * The Radio Amateur Telecommunications Society
; * 206 North Vivyen Street.
; * Bergenfield, New Jersey 07621
; *
; * Telephone: 201-387-8896
; *
; */
;
; System Init for ROM
;
psect text,pure
*INCLUDE RCONFIG.LIB
*INCLUDE STRUCT.LIB
MSYNC EQU 10H
CTS EQU 5 ;SIO RR0 CTS Bit (Mask 20h)
MDCD EQU 08H
MRTS EQU 02H
POWER_FAIL EQU 0150H
GLOBAL CLKBIT, TICKCNT, HDWbss, HDLI
psect text
start: di ;Insure NO int's!!
jp POWER_FAIL ;Power Failure, check memory, etc
jp INIT_HDW ;Set up SDS's based on the machine type
jp INIT_LED ;Init Led's
jp UPD_LED ;Change Led's (toggle)
jp halted ;We are halted...
global amul, brelop, wrelop, csv, cret
RST2: jp (hl) ;for optimizer **********'0010'**************
defm 'AEA PK-'
RST3: jp amul ;for optimizer **********'0018'**************
defm '87/88'
RST4: jp brelop ;for optimizer **********'0020'**************
defm 'VHF '
RST5: jp wrelop ;for optimizer **********'0028'**************
defm 'W2VY'
defb 0
RST6: jp csv ;for optimizer **********'0030'**************
defm 'ROSE'
defb 0
RST7: ex (sp),hl ;for optimizer **********'0038'**************
pop hl
jp cret
tickcnt: defb 12 ;Clock is at 600 hz
defw TBAUD+1 ;Pointer to Terminal baud rate
defw RBAUD+1 ;Pointer to Radio baud rate byte (SCCBI)
ileds: defb 09h ;Initial LED Pattern
defw SDSI0, SDSI1
global SDS0, SDS1
; Initialize the SCC data structures
INIT_HDW:
LD HL,SDSI0 ;Copy from ROM
LD DE,SDS0 ;To RAM
LD BC,SDSILEN
LDIR
LD HL,SDSI1 ;Copy from ROM
LD DE,SDS1 ;To RAM
LD BC,SDSILEN
LDIR
LD A,09
LD C,0F2H
OUT (C),A ;WR 9
LD A,0C0H ;Master Reset for SCC
OUT (C),A
LD A,MSYNC ;PK-87/88 Clock bit (SYNC)
LD (CLKBIT),A ;Save it
LD A,(tickcnt) ;Clock is at 600 hz
LD (TICKCNT),A ;Number of Interrupts/Tick to 10ms
; Radio Port PTT/DCD is always normal
LD HL,0FF02h ;PTTMSK1=MRTS, PTTMSK2=FF
LD (SDS0+PTTMSK1),HL
XOR A
LD B,A ;DCD is Normal - No Toggle
LD (SDS0+DCDTGL),A
; Is the async port on a NetRom back-to-back cable?
LD A,(SDS1+CPORT) ;Async Port
LD C,A ;Port Address
IN A,(C) ;Get RR0 Status
BIT CTS,A ;CTS ON?
JR NZ,1f ;No, Don't Invert RTS and DCD
LD HL,7D00h ;PTTMSK1=00, PTTMSK2=~MRTS
LD B,MDCD ;Toggle DCD Bit
LD A,(SDS1+WR5REG)
OR MRTS ;Set the Async PTT to the right idle State
LD (SDS1+WR5REG),A
1: LD (SDS1+PTTMSK1),HL ;RTS Handling
LD A,B ;DCD Handling
LD (SDS1+DCDTGL),A
LD IY,SDS0
CALL HDLI
LD IY,SDS1
CALL HDLI
RET
LATCH EQU 0F4H ;Address of LED Latch
INIT_LED: ;Enter with (_COLD) in A and B
LD C,LATCH
AND 0C0H ;Make sure we only have 2 bits
SRL A
SRL A
LD B,A
SRL A
SRL A
SRL A
OR B
OR 0C9H ;Turn off Multi bit (Wait Light) and CON
;And CONV, SEND
OUT (C),A ;Do it!
LD (HDWbss+1),A ;Last Write to LEDs
LD A,(ileds)
OR 0C0H ;Turn off Multi bit (Wait Light) and CON
LD (HDWbss),A ;This is where we save the LED status
RET
UPD_LED:
call csv
IN A,(0F8h) ;Tickle Watchdog
LD A,(HDWbss) ;Get LEDS
AND 03FH ;Drop High Bits
SRL A ;Shift LEDs
JP NC,1f ;If no CY, we are OK
OR 20H ;Put lost bit back in...
1: OR 0C0H ;Wait Light OFF and CON LED OFF (To get -12 on Pin 8/RS-232)
LD (HDWbss),A
OUT (LATCH),A ;Update LEDS
LD (HDWbss+1),A ;Last Write to LEDS
jp cret
halted: LD A,(HDWbss+1) ;Get Last Write to LEDS
XOR 80h
OUT (LATCH),A
HALT
XOR 80h
OUT (LATCH),A
RET
GLOBAL SDSI0, SDSI1
SDSI0: DEFB 0 ;Channel number
DEFB 0F3H ;SCC data port
DEFB 0F2H ;SCC control port
DEFW DWAIT0
DEFW TXDELAY0
DEFW SCCAI ;SYNC CONFIG
DEFB SCCAIL ;LEN
DEFB 0 ;Flags
DEFB 069h ;WR5REG (DTR Now On, Port 2)
SDSI1: DEFB 1 ;Channel number
DEFB 0F1H ;SIO data port
DEFB 0F0H ;SIO control port
DEFW DWAIT1
DEFW TXDELAY1
DEFW SCCBI ;8530 Async Config
DEFB SCCBIL ;LEN
DEFB MASYNC+MTIMER+MAFT ;Line for timer
DEFB 068h ;WR5REG DTR is Now ON, RTS Off
ENDC
; Fixed data
; SCC SYNC initialization block.
SCCAI: DEFB 4,0A0H ;X32, SDLC, Sync
DEFB 10,0A0H ;Init CRC, NRZI
DEFB 7,7EH ;Sync Definitition (No S!!t)
DEFB 2,0H ;Interrupt Vector
DEFB 3,0DAH ;8 bit Rx, Enter Hunt, RXCRC, Sync Load Inh.
DEFB 5,68H ;8 Bit Tx, Tx Enable
; next 3 lines are for internal baud rate with external divider for TXC
DEFB 11,66H ;RXC=DPLL O/P, TXC=RTxC, TRxC=O, TRxC Out=BRG Out
RBAUD: DEFB 12,62,13,0 ;Time Constant (1200 Baud) (PCLK/(2*32*baud))-2
; 300 baud = 254, 600 baud = 126, 1200 baud = 62, 9600 baud = 6
DEFB 14,82H ;Set Source=BRG, BR Generator source
; next 2 lines are for external clocks
; DEFB 11,68H ;RXC = DPLL Out, TXC = TRxC, TRxC=IN,
; DEFB 14,0A0H ;DPLL Source = RTxC (x32 clock)
DEFB 5,069H ;DTR Off(7910),8 bitTx,TxEnable,TX CRC Enable
DEFB 3,0DBH ;Same as 3 above, RX Enable
DEFB 14,23H ;Enter Search Mode, Enable BRG
DEFB 15,0D8H ;Enable Interrupts on
DEFB 10H,10H ;Reset External Interupts, Twice
DEFB 1,13H ;Interrupt on Receive and Xmit
SCCAIL EQU $-SCCAI
; SCC ASYNC initialization block.
SCCBI: DEFB 14h ;WR 4 + Reset Ext Intr
DEFB 44H ;16xClk + 1Stop + NoParity
; Internal baud rate generator
DEFB 11,56H ;RXC = BRG, TXC = BRG, TRXC OUT, TRXC=BRG
TBAUD: DEFB 12,14,13,0 ;Time Constant (9600 Baud) (PCLK/(2*16*baud))-2
; 1200 baud = 126, 2400 = 62, 4800 = 30, 9600 = 14
DEFB 14,63H ;Disable PLL, BRG Source, BRG Enable
; External Clocking
; DEFB 11,00H ;TXC, RXC - RTxC Pin
DEFB 3,0C1H ;WR3, 8bit + RxEnable
DEFB 5,068H ;WR5, DTR On + 8bit + TxEnable + RTS Off
DEFB 15,0D8H ;Enable Interrupts on
DEFB 10H,10H ;Reset External Ints
DEFB 1,13H ;Enable rx, tx, ext ints
DEFB 9,9 ;Master Interrupt Enable, Vector Includes Stat
SCCBIL EQU $-SCCBI